Date

PLANNED SCHEDULE

ACTUAL SCHEDULE

July 28

Quantitative Principles (Ch. 1)

July 29

Quantitative principles incl. Amdahl's law + processor perf. Eqn.

August 4

ISA – Addressing modes (App. A)

August 5

ISA – Addr. modes, control flow instructions (App. A)

August 11

ISA – Instruction encoding (App. A)

August 12

Compiler-architecture interactions (App. A)

August 18

Memory Hierarchy Design (App. B)

August 19

MHD: 1-3 optimizations (App. B)

August 25

MHD: 4-5 optimizations (App. B)

August 26

MHD: 6 opt. + 1 adv. Opt.

September 1

MHD (2-4 adv. Opt.) (Ch. 2)

September 2

MHD (5-10 adv. Opt.)(Ch. 2)

September 8

Pipelining intro. (App. C)

September 9

ILP – dependences, hazards, forwarding, brach hazards (App. C)

September 12 (SAT)

MINOR – 1 (Ch.1, App. A, App.B, Ch. 2)

September 15

ILP – Static predictors (Ch. 3)

September 16

Dynamic branch predictors, delayed branches, FP pipe., hazards with deeper pipes(Ch. 3)

September 22

Exception handling in pipelines (Ch. 3)

September 23

ILP – loop unrolling, adv. branch predictors (Ch. 3)

September 29

Register renaming, Tomasulo's algo. (Ch. 3)

September 30

Speculation, VLIW, Multi-issue superscalars (Ch. 3)

October 6

Multi-issue superscalars, BTB, return predictors, Int. Inst. Fetch unit (Ch. 3)

October 7

More on BHT, BTB, speculation issues, limits of ILP (Ch. 3)

October 13

Thread level parallelism: fine-grained, coarse-grained, SMT (Ch. 3)

October 14

Centralized and distributed shared memory architectures, cache coherence problem (Ch. 5)

October 20

Cache coherence: snooping (Ch. 5)

October 21

Snooping, directory-based coherence (Ch. 5)

October 27

Synchronization basics (Ch. 5)

October 28

MINOR – 2 (App.C, Ch. 3)

November 3

Memory consistency models (Ch. 5)

November 4