Textbooks: Computer Architecture: A Quantitative Approach by Hennessy and Patterson, 5th Ed. Chapters to be studied are Chapter 1, Appendix A, Appendix B, Chapter 2, Appendix C, Chapter 3 and Chapter 5.
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Date |
PLANNED SCHEDULE |
ACTUAL SCHEDULE |
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August 4 |
Dependability, Quantitative Principles (Ch. 1) |
Quantitative Principles incl. Amdahl's law and Processor perf. Equn. |
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August 6 |
Quantitative Principles (contd.) (Amdahl's law + CPU time calc.) (Ch. 1) |
ISA – Addressing modes and Control Flow instructions (App A) |
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August 11 |
ISA (Appendix A) |
ISA contd. – Instruction Encoding (App A) |
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August 13 |
Memory Hierarchy Design (App. B) |
Compiler-Architecture Interactions (App A) |
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August 18 |
Memory Hierarchy Design (App. B) |
Memory Hierarchy Design (App. B) |
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August 20 |
Memory Hierarchy Design (Ch. 2) |
6 basic optimizations (1-4) (App. B) |
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August 23 (SAT) |
MINOR – 1 (Ch.1, App. A and App. B) |
No Class |
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August 25 |
Memory Hierarchy Design (Ch. 2) |
6 basic optimizations (4-6) (App. B) |
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August 27 |
Memory Hierarchy Design (Ch. 2) |
Memory Hierarchy Design (1-4 adv. Optimizations) (Ch. 2) |
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September 1 |
Memory Hierarchy Design (Ch. 2) |
Memory Hierarchy Design (5-10 adv. Optimizations) (Ch. 2) |
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September 3 |
Instruction Level Parallelism (App. C) |
Intro. to pipelining with MIPS ISA and 5-stage pipeline (App. C) |
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September 6 |
MINOR – 1 (Ch.1, App. A and App. B) |
MINOR - 1 |
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September 8 |
Instruction Level Parallelism (App. C) |
ILP – Dependences and Hazards, Forwarding (App. C) |
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September 10 |
Instruction Level Parallelism (App. C) |
ILP – Dependences, Hazards, Branch hazards, static predictors (App. C) |
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September 15 |
Instruction Level Parallelism (Ch. 3) |
Dynamic Branch predictors, delayed branches, FP pipeline, hazards with deeper pipelines (App. C) |
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September 17 |
Instruction Level Parallelism (Ch. 3) |
Exception handling in pipelining |
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September 19 |
Memory Hierarchy Design (Ch. 2) |
SRAM, DRAM and its optimizations, VMs and ISA issues for virtualization (Guest Faculty: Ch. 2) |
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September 22 |
Instruction Level Parallelism (Ch. 3) |
ILP – loop unrolling, adv. branch predictors |
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September 24 |
Instruction Level Parallelism (Ch. 3) |
Reg. Renaming, Tomasulo's algo. |
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September 29 |
Instruction Level Parallelism (Ch. 3) |
Speculation, VLIW, Multi-issue superscalars |
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October 1 |
Instruction Level Parallelism (Ch. 3) |
Multi-issue superscalars, BTB, Return Predictors, Int. Inst. Fetch Unit. |
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October 8 |
Instruction Level Parallelism (Ch. 3) |
More on BHT, BTB, speculation issues, limits of ILP |
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October 13 |
Instruction Level Parallelism (Ch. 3) |
Thread Level Parallelism: fine-grained, coarse-grained, SMT, centralized and distributed shared memory architectures, cache coherence problem |
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October 15 |
Thread level parallelism (Ch. 5) |
Cache Coherence protocols: Snooping |
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October 20 |
Thread Level parallelism (Ch. 5) |
Cache Coherence protocols: directory-based + Synchronization basics |
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October 22 |
Thread Level parallelism (Ch. 5) |
Synchronization basics + Memory consistency models |
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October 25 (SAT) |
MINOR – 2 (App.C, Ch. 3) |
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October 27 |
Thread Level parallelism (Ch. 5) |
MINOR – 2 (App.C, Ch. 3) |
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October 29 |
Thread Level parallelism (Ch. 5) |
Review Class |